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SEMI 3D6-0913 - Guide for CMP and Micro-Bump Processes for Frontside Through Silicon Via (TSV) Integration

Volume(s): 3D-IC
Language: English
Type: Single Standards Download (.pdf)
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Status
CURRENT - Supported by the technical committee.


Abstract

This Standard was technically approved by the 3DS-IC Global Technical Committee. This edition was approved for publication by the global Audits and Reviews Subcommittee on July 6, 2013. Available at www.semiviews.org and www.semi.org in September 2013.

 

In order to speed up volume production of 3DS-IC products, a generic middle-end process flow is needed to communicate the frontend and backend processes. The quality criteria and metrology methodology of the key modules such as TSV, chemical mechanical planarization (CMP), and micro-bump are developed to ensure high-yield of the middle-end process. Therefore, this guide provides a generic middle-end process flow to define acceptable TSV and CMP quality criteria as well as to develop methodology and measuring procedures for micro-bump. The guide will provide criteria and common baselines of the middle-end process for related upstream and downstream manufacturers in fabricating 3DS-IC products.

 

This Guide proposes a frontside TSV integration scheme as one of the generic middle-end process flow. The flow includes steps such as TSV formation, RDL formation, CMP, temporary carrier bonding, wafer thinning, micro-bump formation, and carrier debonding.

 

This Guide define acceptable CMP criteria of TSV in terms of dishing, erosion, and voids. CMP criteria can be determined by metrology technology in both contact methods such as: micro profilometer; 4-points resistivity probes; or non-contact methods (e.g., ultrasonic scan mapping, Coherence Interferometry, or other laser-based light scattering detection schemes). TSV formation and reveal are significantly dependent on the performance of CMP process. The outcome of the high CMP quality yields better TSV connectivity.

 

This Guide provides criteria for measurement methodology for micro-bump dimensions, including sampling rate, sampling sites and mapping, reference datum, and survey available metrology tools. The outcome will be an important bridge communication among IC design firms, fabs, and packaging houses. The assumption of wafer-to-wafer (W2W), chip-to-wafer (C2W) and chip-to-chip (C2C) are that testing data is available for known test good die.


Referenced SEMI Standards

SEMI 3D1 — Terminology for Through Silicon Via Geometrical Metrology

SEMI M59 — Terminology for Silicon Technology


Revision History

SEMI 3D6-0913 (first published)


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