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SEMI M62-0413 - Specifications for Silicon Epitaxial Wafers

Volume(s): Materials
Language: English
Type: Single Standards Download (.pdf)
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Status
SUPERSEDED - Replaced by a newer version.


Abstract

This Standard was technically approved by the global Silicon Wafer Technical Committee. This edition was approved for publication by the global Audits and Reviews Subcommittee on February 6, 2013. Available at www.semiviews.org and www.semi.org in April 2013; originally published November 2007; previously published September 2012.

 

NOTICE: This Standard replaced SEMI M2 and SEMI M11 in 2005.

 

Epitaxial silicon wafers are utilized for many integrated circuits and discrete semiconductor devices. To permit common processing equipment to be used in multiple device fabrication lines, it is essential for the dimensions of epitaxial wafers to be standardized.

 

In addition, as technology advances to smaller and smaller dimensions for the elements of high density integrated circuits, it has become of interest to standardize additional properties of epitaxial wafers.

 

These specifications define and provide examples of silicon epitaxial wafer requirements for both discrete semiconductor device manufacture and integrated circuit device manufacture. By defining inspection procedures and acceptance criteria, both suppliers and their customers may uniformly define product characteristics and quality requirements.

 

These specifications cover characteristics of both the substrate (through reference to SEMI M1) and the epitaxial layer, including handling and packaging.

 

The specification for epitaxial silicon wafers for discrete semiconductor device manufacture is specifically directed to silicon homoepitaxial deposits thicker than 25 μm on homogeneous silicon substrates or similar epitaxial wafers that are to be used to make discrete devices. For these wafers, device feature sizes are generally in excess of 1 μm.

 

The primary standardized properties set forth in this specification relate to physical, electrical, and surface defect parameters.

 

Specific requirements for density of selected surface defects and variations of layer thickness and layer net carrier density are included together with AQLs for these properties.

 

In addition, Part 3 of the Silicon Wafer Specification Format for Order Entry, which is included as Table 1, can be used to facilitate inclusion of such additional physical properties and suitable test methods as may be required in the specification.

 

The specifications for epitaxial silicon wafers for integrated circuit applications are restricted to wafers of diameter of 100 mm or greater with epitaxial layer thickness less than or equal to 25 μm.

 

These specifications are specifically directed to silicon homoepitaxial deposits on homogeneous silicon substrates only, for which more stringent uniformity and surface defect criteria are required than for epitaxial silicon wafers for discrete semiconductor applications.

 

The primary standardized properties set forth in this Specification relate to physical, electrical, and surface defect parameters.

 

Specific requirements for density of selected surface defects (Table 2) and variations of layer thickness and layer net carrier density are included together with AQLs for these properties. One type of such defect is localized light scatterers (LLS) such as particles, pits, and other surface defects. A table of equivalent LLS density per unit area and number of LLS within the fixed quality area of a wafer is provided in Related Information 1.

 

In addition, Part 3 of the Silicon Wafer Specification Format for Order Entry, which is included as Table 1, can be used to facilitate inclusion of such additional physical properties and suitable test methods as may be required in the specification.

 

Guides formed by a consensus of viewpoints are provided to suggest a foundation to specify an epitaxial wafer for use in integrated circuit manufacture at advanced design rules. Because these guides are not formal specifications but are suggestions from which a specification can evolve, they are provided in Related Information 2. The required specification is determined by the device and the process design. The usefulness of the guides can be increased by considering them prior to developing a device design or process.

 

The complete EDI Code List for items in the Order Form appropriate to silicon wafers, including epitaxial wafers, remains in SEMI M18.


Referenced SEMI Standards

SEMI M1 — Specifications for Polished Single Crystal Silicon Wafers

SEMI M17 — Guide for a Universal Wafer Grid

SEMI M18 — Guide for Developing Specification Forms for Order Entry of Silicon Wafers

SEMI M33 — Test Method for the Determination of Residual Surface Contamination on Silicon Wafers by Means of Total Reflection X-ray Fluorescence Spectroscopy (TXRF)

SEMI M35 — Guide for Developing Specifications for Silicon Wafer Surface Features Detected by Automated Inspection

SEMI M43 — Guide for Reporting Wafer Nanotopography

SEMI M44 — Guide for Conversion Factors for Interstitial Oxygen in Silicon

SEMI M45 — Specification for 300 mm Wafer Shipping System

SEMI M53 — Practice for Calibrating Scanning Surface Inspection Systems Using Certified Depositions of Monodisperse Reference Spheres on Unpatterned Semiconductor Wafer Surfaces

SEMI M59 — Terminology for Silicon Technology

SEMI M78 — Guide for Determining Nanotopography of Unpatterned Silicon Wafers for the 130 nm to 22 nm Generations in High Volume Manufacturing

SEMI MF95 — Test Method for Thickness of Lightly Doped Silicon Epitaxial Layers on Heavily Doped Silicon Substrates Using an Infrared Dispersive Spectrophotometer

SEMI MF110 — Test Method for Thickness of Epitaxial or Diffused Layers in Silicon by the Angle Lapping and Staining Technique

SEMI MF154 — Guide for Identification of Structures and Contaminants Seen on Specular Silicon Surfaces

SEMI MF374 — Test Method for Sheet Resistance of Silicon Epitaxial, Diffused, Polysilicon, and Ion-Implanted Layers Using an In-Line Four-Point Probe with the Single-Configuration Procedure

SEMI MF398 — Test Method for Majority Carrier Concentration in Semiconductors by Measurement of Wavenumber or Wavelength of the Plasma Resonance Minimum

SEMI MF523 — Practice for Unaided Visual Inspection of Polished Silicon Wafer Surfaces

SEMI MF525 — Test Method for Measuring Resistivity of Silicon Wafers Using a Spreading Resistance Probe

SEMI MF534 — Test Method for Bow of Silicon Wafers

SEMI MF657 — Test Method for Measuring Warp and Total Thickness Variation on Silicon Wafers by Noncontact Scanning

SEMI MF672 — Test Method for Measuring Resistivity Profiles Perpendicular to the Surface of a Silicon Wafer Using a Spreading Resistance Probe

SEMI MF723 — Practice for Conversion Between Resistivity and Dopant or Carrier Density for Boron-Doped, Phosphorus-Doped, and Arsenic-Doped Silicon

SEMI MF1390 — Test Method for Measuring Warp on Silicon Wafers by Automated Non-Contact Scanning

SEMI MF1392 — Test Method for Determining Net Carrier Density Profiles in Silicon Wafers by Capacitance-Voltage Measurements with a Mercury Probe

SEMI MF1451 — Test Method for Measuring Sori on Silicon Wafers by Automated Non-Contact Scanning

SEMI MF1530 — Test Method for Measuring Flatness, Thickness, and Total Thickness Variation on Silicon Wafers by Automated Non-Contact Scanning

SEMI MF1617 — Test Method for Measuring Surface Sodium, Aluminum, Potassium, and Iron on Silicon and EPI Substrates by Secondary Ion Mass Spectrometry

SEMI MF1726 — Practice for Analysis of Crystallographic Perfection of Silicon Wafers

SEMI T3 — Specification for Wafer Box Labels

 


Revision History

SEMI M62-0413 (technical revision)

SEMI M62-0912 (technical revision)

SEMI M62-0712 (technical revision)

SEMI M62-1111 (technical revision)

SEMI M62-0309 (technical revision)

SEMI M62-1107 (technical revision)

SEMI M62-1105E (editorial revision)

SEMI M62-1105 (first published - replaces SEMI M2 and SEMI M11)


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